DesignWare IP Solutions for AMBA - APB General Peripherals

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APB GENERAL PERIPHERALS

DesignWare IP Solutions for AMBA - APB General Peripherals

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The DesignWare APB General Peripheral components include many of the commonly used AMBA Peripheral bus building blocks. The components are highly configurable providing the design engineer the flexibility to tailor the components to their desired design requirements. Comprehensive subsystems can be quickly assembled using coreAssembler, an included graphical based subsystem assembly tool. coreAssembler automates the subsystem assembly and IP configuration which includes the creation of an initial verification testbench environment enabled by DesignWare Verification IP, thus reducing the time to first simulation.

The DesignWare APB General Peripheral components for AMBA are available in encrypted format as part of the DesignWare Library. RTL source code is available for license separately, on a pay-per-use basis as part of the DWC APB Peripherals license package.

General Purpose I/O pad control peripheral for the AMBA 2 APB bus (DW_apb_gpio)
Support for up to 128 individually configurable signals. Configurable hardware and software control of each signal. Allows memory mapped reading of external I/O port signals. Optional de-bounce logic and metastability synchronization registers. Configurable selection of external ports as interrupt sources.
Configurable system counters, controlled through an AMBA 2 APB interface (DW_apb_timers)
Up to 8 counters with individually configurable widths and programmable reload values. Option to drive counters from asynchronous clocks, with full synchronization performed. Fully featured interrupt interface with configurable interrupt pulse extension.
Configurable high range counter with an AMBA 2 APB interface (DW_apb_rtc)
Supports a count width up to 32 bits. Allows a unique counter clock which may be fully asynchronous with system clock. Read coherency registers for accurate count value sampling. Features interrupt generation from a configurable clock domain.
Programmable controller for the remap and pause features of the AMBA 2 AHB interconnect (DW_apb_rap)
Allows safe programmable control of the remap feature of the DW_ahb. Supports forcing the DW_ahb bus into a low power mode with the pause feature. Performs reset signal monitoring on a configurable number of interrupts.
Programmable watchdog timer peripheral for the AMBA 2 APB Bus (DW_apb_wdt)
Programmable timer width and timeout value. Programmable reset pulse or interrupt generation on timeout event. Support for an external clock to drive the timeout counter. Prevents accidental counter restarting and device disabling Verification IP for AMBA 2 AHB/APB and AMBA 3 AXI SystemVerilog, VHDL and OpenVera testbenches to generate bus traffic and check for protocol violations. Monitors provide extensive reports to show functional coverage of the bus protocols.
Verification IP for AMBA 2 AHB/APB and AMBA 3 AXI
SystemVerilog, VHDL and OpenVera testbenches to generate bus traffic and check for protocol violations. Monitors provide extensive reports to show functional coverage of the bus protocols.

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