| User Papers |
| A1 - RTL Synthesis |
DC-G Evaluation on a Full Chip Device
Author(s): Giuseppe Fornaciari [ST-CCI-Printer] |
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Synthesis strategies to Enable Accurate Critical Path Selection in Nanometer Technologies
Author(s): Bettina Rebaud [CEA-LETI] |
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| A2 - Physical Implementation with IC Compiler |
Multimode Multicorner Optimization on 45nm IP Using ICC
Author(s): Eric Ponsot [Texas Instruments] |
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Zroute Usage on High Density ARM IPs Implementations
Author(s): Alain Sermesse [ARM, Inc.] |
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| A3 - Analog Mixed-Signal Verification Methodologies |
Mixed-Signal Integration Methodology from IP to SoC
Author(s): Patrice Vado, Mghith Mehdi [Texas Instruments] |
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Smart AMS SoC Verification Flow with HSIMplus, XA & Spice Explorer
Author(s): Alessandro Valerio, Pierluigi Daglio, Luca Buratti, Claudia Castelli, Sergio Pelagalli [STMicroelectronics] |
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| A4 - SystemVerilog Testbench |
SystemVerilog Verification: Ramping-up from IP, through Subsystem, to Chip Level
Author(s): Fabien Camus, Jerome Bombal [Texas Instruments] |
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VIP-VMM Based NoC Verification Flow
Author(s): Carlo Spitale [Arteris] |
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| B1 - Test |
Low-Power Oriented Volume Diagnosis on Yield Losses Depending on Chain Failures
Author(s): Olivia Riewer, Davide Appello [STMicroelectronics], Salvatore Talluto [Synopsys, Inc.] |
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Simulation-Based Transition Fault Flow
Author(s): Patrick Richier [ST-Ericsson] |
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TetraMAX Power Aware ATPG Correlation Study with PrimeTime-PX
Author(s): Saverio Graniello, Swapnil Bahl, Akhil Garg, Roberto Mattiuzzo, Matthieu Sautier [STMicroelectronics], Alfredo Conte, Salvatore Talluto [Synopsys, Inc.] |
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| B2 - Sign Off |
Variation-Aware Analysis Using PrimeTime-VX
Author(s): Nicolas Verkinderen, Arvind NV, Ajoy Mandal, Hariprasad TT, Sandeep P, Ananth Somayaji, Abhishek Misra, David Colin [Texas Instruments] |
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| B3 - Analog Full Custom Design with Custom Designer |
Enabling Asynchronous Design with Standard Layout Tools
Author(s): Christophe Scarabello [Tiempo] |
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| B4 - Low-Power Verification |
MVSIM Experience on Next Generation Wireless Digital SoC
Author(s): Frederic Hunsinger [ST-Ericsson] |
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| C2 - Physical Implementation with IC Compiler |
High Performance IP Implementation with IC Compiler
Author(s): Arnaud Rayer, Frederic Nyer [STMicroelectronics], Jean-Hugues Bosset [ST-Ericsson] |
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ICC Experience on Multi Voltage and Reduced Metal Stack Design
Author(s): Daniela Di Giovanni, Dominico Arena [STMicroelectronics], Giuseppe Contarino [Synopsys, Inc.] |
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| C3 - Transistor Level Advanced Verification |
Advancements in Smart Power Applications Verification with XA
Author(s): Branimir Ivetic, Claudio Vignati, Lyes Djama [STMicroelectronics], Carlo Borromeo [Synopsys] |
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Top-Down Electrical Verification of Mixed-Signal Power Management Circuits with HSIM CircuitCheck
Author(s): Vincent Bligny [ST-Ericsson] |
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| C4 - System and Prototyping |
FPGA-Based SoC HDTV Prototyping Methodology with the Confirma Platform
Author(s): Philippe Damalix, Samuel Fournier, Bruno Denis, Laurent Chalet [STMicroelectronics] |
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OSCI TLM2 Based Virtual Platforms: An Interoperability Trial between ST TAC Platform and Synopsys DesignWare System-Level Library
Author(s): Laurent Maillet-Contoz [STMicroelectronics] |