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Expediting Design Schedules with DC Explorer - Qualcomm’s Experience
Learn how DC Explorer enables early RTL exploration leading to a better starting point for RTL synthesis and accelerates design implementation.
Matt Baker, Staff Engineer, Qualcomm; Sandra Ma, Sr. Director, Corporate Application Engineer, Synopsys; Liz Chambers, Product Marketing Manager, Synopsys
Nov 01, 2011 | | | Meet Your Schedule with New ECO Verification and Other Enhancements in Formality
Hear about the new ECO Verification capabilities in Formality and other key new features, including its low power library checker, ease of use improvements and runtime enhancements.
Mark Patton, Product Marketing Director, Synopsys; David Low, Corporate Applications Engineer, Synopsys
Oct 27, 2011 | | | Lighter, Easier and More Flexible Approaches for Multi-Voltage Low Power Design Specification
In this webinar you will learn how various ways of describing power intent with IEEE 1801 (UPF) can help you achieve more efficient low power designs. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Somil Ingle, Corporate Applications Engineer, Synopsys; Mary Ann White, Product Marketing Director, Synopsys
Oct 12, 2011 | | | Using TetraMAX Diagnostics and Yield Explorer for Rapid Failure Analysis
Learn how TetraMAX ATPG and Yield Explorer provide a fully automated diagnostics solution for isolation of silicon defects and analysis of systematic yield issues.
John Kirkland, CAE Manager, Synopsys; Girish Patankar, Principal Engineer, Synopsys; Cy Hay, Technical Marketing Manager, Synopsys;
Jun 28, 2011 | | | Volume Diagnostics for Rapid Yield Ramp at Nanometer Nodes
Learn how Yield Explorer, Synopsys' unique design-centric yield analysis solution, can help you accelerate yield ramp for your next device.
Dr. Thomas W. Williams, Retired Synopsys Fellow and Adjunct Professor, University of Calgary; Sagar A. Kekare, Group Manager, Product Marketing, Manufacturing Yield Management, Synopsys
May 03, 2011 | | | Harness the Power of SystemVerilog with Design Compiler to Increase Productivity
Learn how the use of SystemVerilog constructs can result in concise, portable RTL that is easier to maintain and consistent with verification requirements.
Liz Chambers, Product Marketing Manager for Design Compiler, Synopsys; James Argraves, Corporate Applications Engineering Manager for HDL Compiler, Synopsys
Apr 27, 2011 | | | Reduce Power Consumption 30% with Advanced Synthesis Techniques
In this webinar you will learn how new advances in clock gating and voltage threshold (Vt) optimization available in Design Compiler can reduce your dynamic and leakage power by 10-30%. You will also have the opportunity to engage in an interactive Q&A session following the technical presentation.
Mary Ann White, Product Marketing Director, Synopsys and Rishi Chawla, Sr. Application Engineering Manager, Synopsys
Apr 14, 2011 | | | Successful Formality Equivalency Checking for Low-power Designs – Tips from the Experts
Learn from the expert how to successfully complete low power EC faster, and quickly address verification issues, with UPF in Formality.
Bob Hatt, Corporate Applications Engineer, Synopsys
Mar 15, 2011 | | | Utilizing Design Compiler to Double Synthesis and P&R Productivity
See how new Design Compiler 2010 technologies double the productivity of synthesis and P&R by enabling RTL designers to perform floorplan exploration while still in synthesis.
Sandra Ma, Sr. Director, Corporate Application Engineer, Alak Ghosh, Staff Corporate Application Engineer Webinar
Jul 22, 2010 | | | New Enhancements for Debugging Inconclusive and Non-Equivalent Verifications in Formality
This webinar will address what to do when faced with an inconclusive for non-equivalent design in Formality.
Common types of failures will be discussed as well as suggestions for resolving them. New features in Formality 2010.03 will be presented which help the designer quickly identify the sources of the issue and makes recommendations on how to resolve them. Recent Formality low power enhancements will also be discussed.
Mitch Milner, R&D Group Director of Formal Verification
Jun 24, 2010 | | | Static Verification Throughout the Low Power Design Flow
Learn how MVRC and Formality tools complement each other to statically verify your design from RTL to transistors.
Krishna Balachandran, Director of Product Marketing, Synopsys; Prapanna Tiwari, Staff CAE, Synopsys; Bob Hatt, Staff CAE, Synopsys
Apr 28, 2010 | | | Reducing the Cost of Pin-Limited Test Using DFTMAX Compression
Designers are increasingly adopting design-for-test methodologies that limit the number of pins allocated for manufacturing test. During this technical webinar, we will examine what is driving this trend and how you can use new capability in DFTMAX compression to reduce the cost of pin-limited test for your designs.
Adam Cron, Principal Engineer, Synopsys; Girish Patankar, Senior R&D Manager, Synopsys
Apr 21, 2010 | | | Design Compiler 2010: Double the Productivity of Synthesis and Place & Route
Learn about a new capability in Design Compiler that allows RTL designers to perform floorplan exploration from within the synthesis environment to efficiently achieve an optimal floorplan. Hear about Design Compiler’s new scalable infrastructure tuned for multicore processors yielding 2X faster synthesis runtimes on quad-core compute servers.
Janet Olson, Sr. Director, R&D, Synopsys; Sandra Ma, Sr. Director, Corporate Applications Engineer, Synopsys
Apr 20, 2010 | | | Successful Equivalence Checking of Highly Optimized DC Ultra Designs
Join us for an in-depth technical webinar focused on how to achieve successful verification on high-performance designs compiled with DC Ultra.
Mitchell Mliner, Synopsys
Apr 21, 2009 | | | Accelerate your design closure with DC Ultra
Join this webinar to hear directly from senior product team members on how you can achieve superior results faster utilizing sophisticated optimizations of DC Ultra.
Sandra Ma, Synopsys; Janet Olson, Synopsys
Apr 21, 2009 | | |
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