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Enabling 20nm Design: A Foundry and EDA Perspective
TSMC and Synopsys will jointly present some of the key design and manufacturing challenges at 20nm process technology. They will highlight the need for early collaboration between EDA, customers and the foundry to ensure a smooth path to tape-out and first-time silicon success.
Willy Chen, Department Manager, Design Methodology & Service Marketing Program R&D, TSMC; Dr. Tong Gao, Synopsys Fellow, Synopsys
May 01, 2012 | | | Efficient Clock Distribution: A Critical Factor in Design Performance
Synopsys and LSI jointly present on designing today’s high frequency, low power clocks. LSI will present their perspective on the challenges of clock distribution and Synopsys will focus on the solutions that enable designers to achieve the best QoR and lowest power at today’s advanced technology nodes.
JC Parker, Senior Director of Design Tools and Methodologies, LSI; Dennis Ding, R&D Director, Synopsys
Apr 04, 2012 | | | Addressing Challenges at 20nm: A Foundry and EDA perspective
Synopsys and Samsung jointly present some of the key challenges of designing and manufacturing at 20nm. Learn about solutions that address these challenges.
KK Lin, Director, Foundry Design Enablement, Samsung; Tong Gao, R&D Fellow, Synopsys
Oct 24, 2011 | | | 28nm Silicon and Design Enablement – A Foundry and EDA Vendor Perspective
In this final webinar of the 32/28nm design series, Synopsys and GLOBALFOUNDRIES share their perspectives on 28nm process technology and design enablement and 32/28nm design solutions respectively.
JC Lin, Vice President of Engineering, Synopsys and Walter Ng, Vice President, IP Ecosystem, GLOBALFOUNDRIES
Oct 13, 2010 | | | Manufacturing-Aware Routing at 32/28nm
Considering yield as one of the objectives during design has become a necessity at the 32/28nm node. In this webinar, you will learn techniques for addressing manufacturing during routing with IC Compiler’s Zroute technology which considers manufacturability as a routing objective.
Dr. Tong Gao, Synopsys Fellow, Synopsys; Yukti Rao, Product Marketing Manager, Synopsys
Aug 11, 2010 | | | Realizing Today’s 32nm and Beyond Large Capacity Designs
Synopsys Design Planning R&D will highlight the latest hierarchical design exploration and planning technology available in IC Compiler for handling today’s large 32/28nm designs.
Thomas Andersen, Director of R&D, IC Compiler, Synopsys; Mark Bollar, Director of Product Marketing, IC Compiler, Synopsys
Jul 28, 2010 | | | Eliminating Late-Stage DRC Surprises with In-Design Physical Verification
Third in the In-Design technology series featuring several high productivity in-design physical verification flows with IC Validator, including Automatic DRC Repair and Pre-Routing Verification – all from within IC Compiler.
Kerstin McKay, CAE Director, Physical Verification, Synopsys
May 05, 2010 | | | In-Design for Faster Design Closure
First in a series addressing 32/28nm sign-off bottleneck challenges and the solutions best suited to mitigate these challenges. Learn how Synopsys’ In-Design solutions make it possible for place-and-route engineers to accelerate design closure by enabling signoff analysis from within the implementation flow.
Dan Page, Vice President of R&D, Implementation Group, Synopsys
Mar 02, 2010 | | | In-Design PV for Faster Time-to-Tapeout
Synopsys’ physical design and verification technologists will show you how in-design physical verification combines timing awareness and signoff accuracy to speed up your tapeout schedule.
Kerstin McKay, CAE Director, Physical Verification products, Synopsys
May 20, 2009 | | |
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