Overview
IC Compiler is an integral part of the Synopsys Galaxy™ Design Platform that delivers a complete design solution, including synthesis, physical implementation, low-power design, and design for manufacturability (DFM). IC Compiler is a single, convergent, chip-level physical implementation tool that includes flat and hierarchical design planning, placement and optimization, clock tree synthesis, routing, DFM, and low-power capabilities that enable de¬signers to implement today's high-performance, complex designs. Widely adopted and recognized as the industry standard for physical implementation, IC Compiler provides best-in-class quality of results (QoR), strong signoff correlation, and powerful DFM capabilities.

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IC Compiler - A Comprehensive Solution

• IC Compiler uses Extended Physical Synthesis (XPS), a significant capability that extends physical synthesis to full place-and-route. XPS enables faster turnaround time (TAT) as well as better QoR, measured in terms of the complete cost vector — timing, area, power, signal integrity, routability, and yield.
• IC Compiler is tightly correlated to the industry-standard signoff solutions—PrimeTime® SI and StarRC™. Additionally, it utilizes these signoff engines to achieve fast, accurate signoff driven design closure during the final changes of physical design implementation. Signoff driven design closure further increases design predictability.
• IC Compiler provides a comprehensive DFM solution that concurrently optimizes for yield with timing, area, power, test, and routability. IC Compiler increases manufacturability of the design, optimizing both functional and parametric yield.
• IC Compiler with concurrent hierarchical design enables powerful design planning and chip-level analysis features to handle large, complex designs. Providing early analysis and feasibility exploration, IC Compiler delivers smaller die size and achieves predictable design closure to reduce the cost of design.
• IC Compiler with Zroute technology utilizes advanced routing algorithms, concurrent DFM optimizations and multithreading to deliver a combined speed increase of more than 10X in routing.

QoR
XPS is an innovative technology in IC Compiler that unifies synthesis, placement, clock tree synthesis, and routing to deliver increased QoR, measured in terms of the complete cost vector — timing, area, power, signal integrity, routability, and yield. New technologies like concurrent multi-corner multi-mode (MCMM) optimization, enhanced signal integrity capabilities, and physical datapath enable designers to meet aggressive QoR targets for large, complex chips.

Figure 1. Physical datapath increases predictability and reduces power

Turnaround Time
IC Compiler provides the fastest path to results. This is achieved using powerful design planning capabilities, complete convergence throughout the design stages, and a seamless RTL-to-GDSII flow.

• Design Planning: IC Compiler includes complete flat and hierarchical design planning capability and delivers multimillion- instance design capacity. Because concurrent hierarchical design is native in IC Compiler, designers are able to concurrently carry out planning and implementation within a single environment, leveraging IC Compiler's common engines, Tcl, GUI, and single timer from planning through physical implementation to tapeout. It is intended to be used for both a fast exploration of the design to reduce die size and to implement a final, optimized and detailed floorplan. MinChip technology in IC Compiler allows designers to automatically implement the smallest routable die for their design while power network synthesis and analysis automatically creates a power network that meets IR drop requirements.


Figure 2. Thermal map based on PNS and IR drop

• Correlation to Signoff: IC Compiler is tightly correlated to the industry standard signoff tools, PrimeTime SI and StarRC. IC Compiler shares delay calculation modules with PrimeTime and PrimeTime SI, including cell delay, Arnoldi wire delay, Composite Current Source (CCS) models, as well as features like Clock Reconvergence Pessimism Removal (CRPR), and On-Chip Variation (OCV) to achieve the highest correlation to signoff in the industry. In the final stages of design closure IC Compiler utilizes PrimeTime SI and StarRC to incrementally deliver signoff assured design results within the implementation flow.
• Design Convergence: IC Compiler, in combination with Design Compiler® Ultra topographical technology, provides the strongest correlation between synthesis and physical implementation for a highly convergent RTL-to-GDSII flow by leveraging a single timer throughout the flow. IC Compiler is based on the industry-proven Milkyway™ database, making the design flow faster, more efficient, and more predictable. This is critical to improving turnaround time and enables designers to focus on differentiating design features instead of debugging data transfer issues.


Figure 3. Early analysis facilitates faster design convergence

• Multi-Corner Multi-Mode (MCMM): Concurrent MCMM-aware placement, routing, and optimization transformations dramatically reduce TAT for large, complex chips. Intelligent optimization is driven by timing, area, power, signal integrity, routability and yield cost factors that are measured concurrently across all scenarios. IC Compiler's MCMM solution eliminates the ping-pong effects of sequential or quasi-MCMM approaches used by other vendors.
• Zroute Technology: Zroute technology in IC Compiler utilizes advanced routing algorithms and multi-threading capability to take full advantage of the newest multi-core computer platforms delivering 10X speedup with mainstream platforms. Zroute's modern architecture incorporates state-of-the-art routing technology, such as native soft rules to enable litho-friendly routing and avoid manufacturing problems. Employing concurrent DFM optimization techniques, Zroute simultaneously considers the impact of manufacturing rules, timing and other design goals to deliver the highest QoR along with improved manufacturability.

Figure 4. IC Compiler Zroute technology for super-fast, DFM-friendly routing

Cost of Design
IC Compiler allows designers to utilize a variety of techniques to meet timing, power, area, routability and yield goals. This reduces the cost of design and increases predictability.

• DFM: IC Compiler offers the only complete solution available to optimize for yield and manufacturability. Concurrent DFM optimizations reduce the number of remaining single vias, and the critical area for higher yield while still meeting timing QoR.
• Power: Power management has become an extremely important design issue. Advanced multi-voltage designs for wireless, mobile, and consumer applications must deliver maximum performance while minimizing power. IC Compiler and the Galaxy Design Platform deliver a complete low-power flow to handle complex power-sensitive applications from wireless to multi-million-gate graphics designs.
• Design for Test (DFT): IC Compiler as part of the Galaxy flow provides a comprehensive test automation solution that offers SoC designers the fastest and most cost-effective path to high-quality manufacturing tests and working silicon. Fully-integrated DFT MAX, next-generation test compression and synthesis technology achieves high compression without affecting the test coverage, functionality, timing, or power requirements of the design.

Figure 5. CAA map before and after wire spreading in IC Compiler

Figure 6. Via optimization in IC Compiler

Ease of Use
IC Compiler advances ease-of-use with core commands (place_opt, clock_opt, and route_opt) to deliver best out-ofthe- box results. The IC Compiler GUI provides intuitive and easy-to-use features that enable designers to resolve issues at all design stages. The GUI enables fast analysis, visualization, debugging and repair features.

All of these shared technologies and key advances in IC Compiler enable the Galaxy Design Platform to deliver the best QoR in terms of timing, area, power, routability, testability and yield as well as faster TAT and a predictable path to first-silicon success. Today designers are using IC Compiler successfully to tape out numerous complex, high-performance, and low-power designs at 130nm to 45nm and below geometries.

Features

• High throughput for designs in mainstream silicon technologies
• High performance for advanced silicon technologies
• Comprehensive optimization capabilities meet timing, area, power, signal integrity, routability and yield objectives
• Predictability during the implementation process
• Single timer
• Complete netlist-to-GDSII solution for best QoR and TTR
• Signoff
• Highly correlated with golden signoff solutions: PrimeTime SI and StarRC
• Shares common infrastructure and technologies with PrimeTime, such as Arnoldi, OCV, CRPR, CCS, common cell delay calculation and SDC constraints to ensure tight correlation
• Improves TTR by eliminating unnecessary margins
• Speeds design closure by using exact signoff timing and extraction information

Figure 7. Register grouping using power-aware placement reduces power

Figure 8. Design before scan ordering	Figure 9. Design after scan ordering

• TAT
• Concurrent MCMM optimization
• Tight correlation with Design Compiler topographical technology
• Physical datapath enables dramatic improvement in productivity for datapath logic implementation and provides predictable results in timing, area, and power
• Robust crosstalk flow during all stages; detects and fixes crosstalk violations
• Power
• Support for multi-voltage designs during design planning, synthesis, placement, clock tree synthesis, routing, and chip finishing stages
• Complete multi-voltage support
• Advanced algorithms deliver high-quality dynamic and leakage optimization results
• Power-aware placement technology groups registers to reduce dynamic power
• Support for complex clock gating in clock tree synthesis
• Low-power, SI-aware CTS
• Signal electromigration analysis and repair significantly improves design reliability
• DFM
• Complete support for advanced design rules
• Soft rule support
• Cell and route-based yield optimizations
• Critical Area Analysis (CAA)
• Optimization of critical areas through wire-spreading/widening during global route, track assignment anddetailed routing
• Automated, timing driven multi-pattern via selection
• Timing-driven metal fill
• Staggered metal fill
• Litho-friendly routing
• Automated lithography hotspot fixing
• Tight integration with Hercules DRC/LVS checker
• Design Planning
• Concurrent hierarchical design
• Complete design planning solution for hierarchical and flat designs
• MinChip technology enables the smallest routable die
• Early analysis and feasibility exploration capabilities
• Million-instance design capacity
• Complete multi-voltage flow with MTCMOS support
• Power Network Analysis (PNA), Power Network Synthesis (PNS), and power-pad synthesis capabilities
• Timing-driven automatic macro placement
• DFT
• Physically optimized scan chains deliver predictable timing closure
• Physical test-optimized flow with support for DFT Compiler and DFT MAX features using scanDEF interface
• QoR
• Common engines throughout the flow
• Single timer
• Innovative XPS optimization capabilities in timing, area, DFT, power, routability and yield ensure best QoR
• Physical datapath delivers QoR by adding controllability and predictability to the physical implementation for effective datapath management in high speed designs


Figure 10. Critical path cross-highlighting enables faster debugging

• Ease of Use
• Core commands for placement, CTS, and routing
• Tcl support throughout
• GUI
• Powerful features enable design analysis, visualization, debugging, and fixing
• Cross-referencing between logic vs. physical analysis
• Clock tree synthesis skew and latency analysis
• Hierarchical clock tree browser
• Power Network Analysis (PNA)
• Visual maps for Worst Negative Slack (WNS)/congestion/cell density/scan/leakage power/dynamic power/total power and more
• Critical Area Analysis (CAA)
• CMP thickness and CMP hot spots
• Fast physical data analysis and editing
• PrimeTime-style analysis (path inspector)

Interfaces

• Library Interface
• Reads LIB synthesis library containing functionality, timing, and design rule constraints
• Reads Milkyway (MWY) physical library describing technology and cell outlines
• Reads LEF, Technology File (TF) format
• Inputs
• Verilog netlist
• SDC, DEF, SPEF, SBPF
• Several user-level commands are provided for specifying and modifying the floorplan
• Outputs
• Verilog netlist
• SDC, DEF, SPEF, SBPF
• GDSII
• User Interfaces
• TCL- or GUI-based user interface
• All Design Compiler reports enhanced with physical information; additional reportsand commands enable analyzing layout and checking consistency of libraries and input files
• Supported Platforms
• AMD64, Sparc64, Linux32 4.0, Suse 32, Suse 64