Synopsys FPGA-Based Prototyping Solution Brings It All Together
The Synopsys FPGA-based prototyping solution is a complete hardware-assisted verification environment based on our HAPS® High-performance ASIC Prototyping System ™ which is supported by a comprehensive software flow including Synplify® FPGA synthesis, Certify® design partitioning, and Identify® interactive debugging software.
Synopsys’ High-Speed Time Division Multiplexing (HSTDM) technology combined with high-speed HapsTrak II connectors ensures inter-chip communication is not a bottleneck. The fastest FPGA silicon, sophisticated PCB technology and advanced power and heat management ensures a stable and repeatable platform suited to all design types. The unique Universal Multi-Resource Bus (UMRBus) improves designer productivity by extending the rapid system prototyping environment and enabling it to be leveraged earlier in the design cycle. The UMRBus also enables remote hardware access, data streaming, co-simulation, transaction-based verification and links both our virtual prototyping and FPGA-based prototyping environments utilizing the industry standard SCE-MI interface.
- Benefits of the Synopsys FPGA-based prototyping solution include:
- Early embedded software development speeds design schedules by 3-6 months
- Easy integration of pre-tested DesignWare IP components eliminates the need for designers to verify their IP
- Modular platform enables reconfigurability and reuse across multiple projects
- Proven solution with over 2500 systems used by more than 300 customers
- High-performance prototyping system allows developers to perform real-world testing with real-world high-speed interfaces
- Low cost and proven prototyping technology reduces schedule risk and shortens product development time for faster time-to-market
- Easily and cost effectively deployable to software development teams worldwide
- Co-simulation capabilities enable faster development and greater debug visibility
- Transaction-based verification allows the prototyping system to be used as a model in system-level virtual platforms
- Immediate availability of affordable, reliable, flexible, and expandable prototyping hardware
- Flexible architecture supports multiple systems and high-speed interfaces
Synopsys’ FPGA-based prototyping solutions enable pre-silicon embedded software development and hardware/software co-verification of complete systems and subsystems at near real-time operating speeds using real-world interfaces. The HAPS® High-performance ASIC Prototyping System™ is designed to support all of your ASIC prototyping needs, including hardware/software co-development, proof-of-concept studies, IP development and end-user evaluations. HAPS FPGA-based prototyping system capabilities include:
- Flexible, scalable and expandable system architecture – maximizes the reusability for multiple projects
- Best-in-class quality and reliability – ensures the highest system performance and stability
- HapsTrak standard – I/O connector standard that allows for backward and forward compatibility with previous and future generations of HAPS FPGA-based prototyping systems
- High-speed Time-Domain-Multiplexing (TDM) – high-speed interconnect multiplexing increases bandwidth limiting effective capacity on FPGAs
- Programmable interconnect – automatic architectural trade-offs
- Advanced verification functionality – includes co-simulation, transaction-based verification, and fast Universal Multi-Resource Bus (UMRBus) interface for high-speed design interaction and monitoring
- DesignWare IP Portfolio – pre-tested IP configurations
Visit the HAPS FPGA-based prototyping webpage for more information.
CHIPit Automated FPGA-Based Prototyping
The CHIPit automated FPGA-based prototyping systems provide functional verification and validation for the entire SoC and ASIC design process. Throughout the verification process CHIPit gives design engineers superior speed and flexibility for hardware verification, pre-silicon software development, and system validation. The multifunctional system can be used in multiple verification modes, including cycle/event-based co-simulation, SCE-MI compliant transaction-based verification and in-circuit prototyping to significantly reduce the overall design and verification time. The patented programmable interconnect architecture in combination with a comprehensive software suite enables more automation and the highest productivity for design implementation, verification and debug.
Visit the CHIPit automated FPGA-based prototyping webpage for more information
Synopsys’ FPGA-based prototyping software tools provide designers with an easy-to-use flow that is fully integrated with the HAPS hardware products. Together, our FPGA-based prototyping hardware and software products help designers to dramatically accelerate functional verification of ASIC, ASSP and SoC designs.
FPGA Implementation
The Synopsys FPGA design solution comprises high-quality, high-performance, and easy-to-use FPGA implementation. Designers using the Synplify Premier FPGA design tool gain fast time-to results for complex FPGAs, area optimization for cost and power reduction, incremental and team design capabilities for faster FPGA design development. The Synopsys FPGA design tools provide additional value by offering DesignWare® IP integration, links to high-performance functional verification with VCS and an ASIC compatible synthesis flow for that works seamlessly with the HAPS FPGA-based prototyping systems. For more information visit the FPGA Implementation section of our website.
Design Implementation and Partitioning
The Certify software is the leading implementation and partitioning tool for ASIC designers who use FPGA-based prototypes to verify their designs. Certify provides a quick and easy method for partitioning large ASIC designs onto multi-FPGA-based prototyping systems and includes powerful features that make it easy to adapt to existing device flows and offers additional and exclusive features in combination with the HAPS prototyping solutions. For more information visit the Certify Multi-FPGA partitioning and implementation product page.
Debugging
The Identify ® RTL debugger allows users to instrument their RTL and then, still at the RT-Level, debug the implemented FPGA on live, running hardware. The Identify FPGA debug software verifies a design in hardware, similar to simulation – only much faster and with in-system stimuli. For more information visit the Identify RTL Debugger product page
Co-Simulation
The HAPS Co-Simulation environment is a powerful tool that provides a direct link between selected system parts running in the RTL Simulator and Design Under Test (DUT) running in the HAPS prototyping system. This allows, for example, to move the DUT of a verification environment into the hardware while still keeping the (non-synthesizable) testbench in the simulator, or to run a stable part of the SoC in the hardware while still keeping the rest in the simulator for higher debug visibility. The HAPS co-simulation interface works with all popular RTL simulators like Synopsys VCS®, Cadence NC-Sim, and Mentor Graphics ModelSim®.
Transaction-Based Verification
The HAPS transaction-based environment enables users to stimulate the Design Under Test (DUT) from the host side by a C/C++, SystemC or SystemVerilog based testbench at the transaction level instead of the signal level. This mechanism accelerates the verification dramatically, because the number of data exchanges between host and hardware are minimized delivering the performance required for software simulation. The HAPS transaction-based interface is based on Accellera’s standard co-emulation modeling interface (SCE-MI) and supports version 1.1 and 2.0, and links to Synopsys’ Virtual Prototyping Solution
FPGA-based prototyping hardware/software flow