- Highlights
- Traffic Generators
- Interconnect Models
- Memory Subsystem Models
- Processor Models
Synopsys Platform Architect supports the broadest commercially available portfolio of pre-instrumented SystemC TLM models for SoC architecture exploration and validation. Synopsys Architecture Design Models enable architects and system designers to efficiently design, analyze, and optimize the performance and cost of multicore SoC architectures in Platform Architect.
The library contains SystemC TLM models of commonly required architectural components including generic traffic generators, AMBA and OCP-IP based interconnects, memory subsystems, and embedded processors, including:
- Traffic Generators
- Generic File Reader Bus Master (GFRBM) for trace-driven traffic generation
- Generic Virtual Processing Unit (VPU) for application task-mapping and task-driven traffic generation
- Interconnect Models
- Cycle-accurate SystemC TLM bus libraries for ARM AMBA® 2 AHB™/APB™, AMBA 3 AXI™ (PL300), and CoreLink™ Network Interconnect (NIC-301)
- Generic approximately-timed SystemC TLM bus libraries for industry-standard OCP-IP and OSCI TLM-2.0
- Memory Subsystem Models
- Generic approximately-timed SystemC TLM memory subsystem models for ARM AXI, OCP-IP, and OSCI TLM-2.0 interfaces
- Cycle-accurate SystemC TLM memory subsystem models for ARM PL172 (AHB), PL310 (AXI), PL340 (AXI), and PL341 (AXI) Primecells
- Processor Models
- Cycle-accurate SystemC TLM processor support packages (PSPs) for ARM, MIPS, and Tensilica processor families
Developed in partnership with leading IP providers including ARM, MIPS and Tensilica, these models are configurable and fully instrumented for performance analysis. In addition, see the DesignWare TLM Library and Virtual Prototyping Models pages for more models that are compatible with our Architecture Design solution. Synopsys can also work with customers to create architecture performance models through our CoStart Enablement Services.