With shrinking process geometries, static and dynamic power are increasing rapidly, forcing designers to use a variety of implementation techniques to control power. MIPS Technologies processor cores designed for low power applications use multiple power modes and employ a Power Manager to ensure correct transitions between these modes. This paper focuses on the verification of the Power Manager in the context of the – MIPS 1004K™ Coherent Processing System (CPS), in which various software and hardware events can control switching of power states. Without exhaustive verification of the Power Manager, the power management functionality of the design cannot be guaranteed. This paper discusses on how we successfully used formal methods to verify the Power Manager.
Kesava R. Talupuru, MIPS Technologies

Power consumption is a critical consideration in modern designs. Customers are demanding higher performance and reliability along with lower system cost. Efficient use of power is a major factor in meeting these demands. Hence, accurate power analysis is essential to achieve de-sign success. This paper describes the power analysis methodology used in our PrimeTime PX evaluation. The test vehicle was a LEON 3FT (fault tolerant) microprocessor device, which is currently in production. Starting with a PrimeTime PX vs. silicon mismatch of more than 30%, we made improvements to the process which, in the end, yielded correlation results within 10% of actual silicon measurements. Strategies for identifying problem areas along with solutions and corresponding correlation improvements are summarized for each issue encountered. Findings and recommendations will be presented in the concluding remarks.
Steve Griffith, Aeroflex

These days, almost every semiconductor chipset uses multiple voltage domains, either to cut leakage or for dynamic power reduction. A common method in multi-voltage designs is to completely shut down entire portions of RTL to save power. The power behavior of these designs is captured in what is referred to as a power intent file, commonly defined using the industry standard IEEE 1801 (UPF) format. This paper describes a hierarchical UPF approach, which will allow you to reuse the UPF files for sub-modules across different products. This paper will also describe how to handle analog macros in the power subsystem in the context of a UPF flow.
Krishna Vittala , Microchip Technology Inc.

An effort to reduce power involves both detailed analysis of the design as well as using techniques available in implementation tools. Detailed metrics also help gauge the effectiveness of any particular technique in the implementation tool. The paper presents a series of metrics – some help RTL designers make better design decisions and some help implementation engineers evaluate the effectiveness of power reduction methods available in IC Compiler™. It then goes through the available methods in IC Compiler, compares the various techniques and methods, and presents comparative results between the techniques. The final results were a dynamic power reduction of 27% and clock tree power reduction of 61%.
Avishek Panigrahi and Arvind Parihar, MIPS Technologies, Inc.

The following paper describes how verification of low power features was done on a hierarchical UPF design with MVRC in pilot usage. The design contains Low Power (LP) measures like shut-off domains using power switches, always-on do-mains, Level Shifters (LS) and retention memories. Infineon’s solutions for UPF qualification on RTL as well as structural, functional, and architectural checks on block-level and top-level using MVRC will be discussed. The paper will conclude with an outlook on how MVRC is planned to be incorporated into the Infineon design flow.
Stefan Rolf, Infineon Technologies

Reduction of power consumption in systems, implemented in deep sub-micron technologies, is fast becoming a delimiting factor. Ideally the consideration of power optimization would be managed as any other design constraint. To-date, however, this has been hampered by the lack of standardization across the EDA domain. As a consequence larger design teams have developed or adopted proprietary solutions to tackle this problem. These solutions lack the efficiency and portability required for an industry-wide acceptance. The Unified Power Format (UPF) is a recent standard for describing the power objectives of a design, which can then be used as optimization constraints for the designs. We show how the low power goals can be described in a simple unified approach using the UPF and how different EDA tools support low power specifications with UPF. We have taped-out three low power designs with UPF flow. The problems encountered during the course, their solutions and workarounds have been described to make the users aware of the advantages and short comings of this emerging flow for describing low power intent.
Serge Durand and Faisal Suleman, Semtech Neuchatel SA

In this paper we present Design Compiler with UPF Flow applied to an Ultra Low Power System on Chip. REISC SoC is targeted as a test-vehicle chip integrating power safe solutions to challenging design goals for biomedical devices and wireless sensors. We use power intent based flow using UPF (Unified Power Format) for a large design delivered at 90nm with 10 power domains, including nested ones, power rails, 4289 retention registers, 882 isolation cells managed through 8 isolation strategies and 8 power table states. The design flow has been customized in order to manage retention registers and macros with incorrect operating conditions. For these reasons it should be considered a real case study.
Elio Guidetti, Giuseppe Notarangelo and Elena Salurso, STMicroelectronics

Today’s deep submicron semiconductor processes offer designers the ability to implement incredibly rich functionality even on small, inexpensive die. However, the resultant power arising from high frequency switching of the tens of millions of transistors to support this rich functionality directly impacts other critical product needs, including battery life, packaging and cooling costs, form factor and reliability. In order to solve this challenge, designers must incorporate low power design techniques throughout the design process causing varying degrees of impact to implementation and verification flows. This article will share the experience of using the industry-standard Unified Power Format (UPF, IEEE1801) - also known as power intent file, understood by all the tools along the design flow - on a complex multi-voltage 45nm design done at STEricsson.
Guilhem Caubit, STEricsson

Increasing complexity of low power techniques demands accurate verification of power network schemes and protection requirements. Also, low power simulations must cover specific risk of introducing functional bugs in the power intent description itself. These considerations led the ST TRnD team to enhance behavioral models of hard macros in order to integrate the multi-rail behavior. The “power-aware” models take benefits of MVSIM and its “Direct Design Connection” feature to guarantee a full validation of the power intent file (UPF) and still remaining usable in traditional digital simulation.
Mohit Jain and Rashna Seli , STMicroelectronics, Pierre-Yves Alla, Synopsys

In a low power design flow based on the Unified Power Format, the UPF is the golden reference of the Power Intent. The UPF usage along the design flow determines two aspects of the Low Power checkers: • First, the validation of the UPF on the RTL to check the coherency of the UPF and the design BEFORE the Synthesis and the Simulations. • Secondly, the check of the Power Intent in the different netlists. MVRC (Multi Voltage Rule Checker) addresses both aspects and was used for a complex 45nm design. In this paper, the concrete usage of MVRC all along the flow will be shown: from the RTL to the low power Signoff.
Frederic Saint-Preux, STEricsson

For test and design for test (DFT), power becomes a major concern because of the high power activity which is required during scan testing. In the past, TetraMAX, the Synopsys ATPG tool, provided a power-aware test pattern generation that performs low-power fill during shift cycles. However, this adjacent fill algorithm was not efficient enough for designs that embed scan compression logic. Knowing that, Synopsys developed a new ATPG low-power algorithm that gives the capability to control the switching activity during scan shift. The new algorithm is ATPG based and doesn't require any design change, allowing to use the new patterns on existing designs to address power issue when they appear on the tester. This technical paper presents our experimental work and the associated conclusions based on the simulation and silicon results on two different designs.
Pascal BLANC, STEricsson, Saverio Graniello, STMicroelectronics, Philippe ROSSANT, Synopsys

Power-gating techniques are implemented in DSP designs to reduce leakage and standby power. Parts of DSPs can be powered down, while others, such as SRAM, cannot, as they are important for state retention. It is crucial to verify that the DSP functions correctly after the power-down cycle is completed. In addition, while some logic is powered down, the rest of the system must continue normal operation. The paper presents techniques that were used to verify the power-down methodology in Fcore4, a 4th generation DSP. The methodology can be reused for future wireless projects using new process technologies.
Prashanth Cherukuri, Mediatek Wireless, Inc

Power and Signal Reliability are becoming major area of concerns for Deep Sub Micron designs with reduced power supplies, reduced metal and via sizes and need for more integration. ARM uses Synopsys HSIMPlus to analyze Power and Signal Reliability issues seen in Memory Compilers.
Satinderjit Singh, ARM

Reducing power in an embedded processor targeted for high performance is becoming a necessity. Using off the shelf standard cell library and memory macros in 65nm, MIPS Technologies and Synopsys worked together to develop an automated design flow for reducing power in the MIPS32® 74K™ family of processor cores. 74K cores are the industry’s first fully synthesizable processors to exceed a GHz performance in a standard 65nm process. This paper describes several techniques employed for simultaneously meeting the performance target while reducing power.
Arvind Parihar Avishek Panigrahi, MIPS Technologies, Inc.

This paper will introduce a systematic approach of reducing power in complex clock-trees using IC Compiler’s low-power CTS (Clock Tree Synthesis) feature. Apart from discussing the various techniques in low-power CTS in ICC, this paper will also formulate a guideline of pre-analysis of a design during P&R (Place & Route) to identify the best method suited for clock-tree power reduction and how to achieve that using IC Compiler. Recommendation will also be provided on how to correlate the estimated clock-tree power in IC Compiler with sign-off (PT-PX). The goal of this paper is to guide the SoC designers to effectively use IC Compiler for clock-tree power reduction.
Hong Li, Narayanan Thondugulam, Santiago Fernandez-Gomez, Apple Shubharthi Datta, Synopsys, Inc.

Power gating is a valuable technique for reducing standby power in portable applications and comprises power rail switching of subsystems to cut leakage power. Power gating at the hardware level is now well supported in Synopsys design and verification tools, and the new UPF aware design flows are able to build on these. However from a system level design perspective inferring power gating, interface isolation and optionally state retention is not enough. This paper describes power management approaches for power gating with due attention to clocks, resets, testability and safe power sequencing - based on silicon proven results.
David Flynn, ARM

There are various strategies for leakage optimization and the optimization can be done at various stages of the flow: library development, synthesis, layout and timing closure. This paper describes a synthesis approach using hybrid-libraries and Vt-bucketing which gives much better leakage optimization than traditional synthesis strategies.
Sandip Patra, Broadcom Corporation

In modern digital ICs, the increasing demand for performance and throughput requires operating frequencies of hundreds of megahertz, and in several cases exceeding the gigahertz range. Following the technology scaling trends, this request will continue to rise, thus increasing the electromagnetic interference (EMI) generated by electronic systems. The enforcement of strict governmental regulations and international standards, mainly (but not only) in the automotive domain, are driving new efforts towards design solutions for electromagnetic compatibility (EMC). Hence, EMC/EMI is rapidly becoming a major concern for high-speed circuit and package designers. The on-chip power rail noise is one of the most detrimental sources of electromagnetic (EM) noise, and it has a large impact on the conducted emissions, since it propagates to the board through the power and ground I/O pads. In this work we investigate the impact of power rail noise on EMI, and we show that by limiting the power rail noise it is possible to drastically reduce the conducted emissions. Moreover, we propose an effective and practical methodology that can be seamlessly integrated into the standard design flows. The experimental results obtained on an industrial microcontroller for automotive applications demonstrate the effectiveness of our approach.
Patrice Joubert Doriol, Cristiano Forzan, Davide Villa, Davide Pandini, Renato Castellan, Daniele Cervini, Mario Rotigni, Giovanni Graziosi, STMicroelectronics Giuseppe Contarino and Egidio Marzorati, Synopsys

This work uses ESP-CV to simulate entire benchmarks using transistor level schematics and post-layout capacitance extraction. By using ESP-CV to translate a schematic netlist into a transistor level Verilog netlist, we can simulation thousands of benchmark cycles in minutes or hours compared with only tens of cycles using a fast spice simulator. This dif-ference in simulation speed allows us to simulate an entire benchmark instead of trying to guess what a good spice simulation window is. This flow has been used extensively for power estimation and optimization of custom macros integrated into Qualcomm's 45nm low power DSPs.
Stephen Bijansky, Bassam Mohd, Baker Mohammad, Qualcomm