The DesignWare® DDR Memory Interface IP is a family of complete system-level IP solutions for system-on-chips (SoCs) requiring an interface to one or more of the broad range of high-performance DDR3, DDR2, DDR, Mobile DDR and LPDDR2 SDRAMs or memory modules (DIMMs). Optimized for high data bandwidth, low power and enhanced signaling features, the complete DesignWare DDR Memory Interface IP solution includes a choice of scalable digital controllers, an integrated hard macro PHY delivering memory system performance of up to 2133 Mbps per bit and verification IP through our DesignWare Verification IP (VIP) Alliance program.

There are four Synopsys DesignWare DDR PHY IP cores to choose from, all of which come with a DFI 2.1 compliant interface to DDR controllers: DesignWare DDR multiPHY IP, DesignWare DDR3/2 PHY IP, DesignWare DDR2/3-Lite/mDDR PHY IP and DesignWare DDR2/DDR PHY IP. The DDR multiPHYs, DDR3/2 PHYs and DDR2/3-Lite/mDDR PHYs are compatible with Synopsys' unique DesignWare DDR PHY Compiler.

There are two types of DDR digital controller IP cores to choose from: DesignWare DDR Memory Controller IP and DesignWare DDR Protocol Controller IP. Synopsys' DesignWare Universal DDR Memory and Protocol Controller IP cores feature a DFI 2.1 compliant interface, low latency and low gate count while offering flexibility of clock frequency ratios between PHY and controller to allow easier timing closure in slower processes and lower latency in faster technologies.