Verification Avenue is the Synopsys technical bulletin for design and verification engineers. This newsletter includes the latest verification product updates, technical articles, a Q&A section, an extensive resource section and an upcoming events calendar. Subscribe now to automatically receive the latest issue!
- November 2007 Issue
- Issue Highlights:
- The VMM Register Abstraction Layer Application
- Trends in Wireless Consumer Electronics Drive the Need for More Complex Mixed-Signal Devices
- Synopsys Introduces DesignWare Port Monitor Verification IP for the AMBA 3 AXI Protocol
October 2006 Issue - Issue Highlights:
- SystemVerilog-OpenVera Interoperability in VCS
- Moving to the Next Level in Verification Productivity and Predictability
- Understanding the Key Elements of a VMM-based Testbench
July 2006 Issue - Issue Highlights:
- SystemVerilog for e Experts: Understanding the Migration Process
- SystemVerilog for Efficient Collection of Coverage Information
- Deploying the Right Tools for Mixed-Signal Simulation
March 2006 Issue - Issue highlights include:
- Pioneer-NTB Enables SystemVerilog Testbench Automation
- DesignWare Verification IP Support of the Verification Methodology Manual (VMM) for SystemVerilog Reduces Time to First Test for Coverage-Based Verification
- Transaction-Level Modeling: SystemC and/or SystemVerilog
June 2005 Issue - Issue highlights include:
- The Formality Equivalence Checker Provides Industry's Best Arithmetic Verification Coverage
- Designing Using the AMBA™ 3 AXI™ Protocol
- Jump-Starting ABV with Assertion Checkers and IP
March 2005 - Highlights:
- Coverage is the Heart of Verification
- Verify More in Less Time with VCS
- Assertion Specification and Usage Requirements
December 2004 - Highlights:
- VCS 7.2: New Features on Every Front
- Successful Mixed-Language Code Coverage with VCS
- Using Vera and Constrained-Random Verification to Improve DesignWare Core Quality
September 2004 - Highlights:
- From Bolt-on to Built-In with VCS
- System Studio: New Release and Virtio Collaboration
- Using Magellan to Diagnose Post-Silicon Bugs, Sun Microsystems
May 2004 - Highlights:
- Integration of Vera and System Studio
- Architectural Modeling for AMBA-Based Design, ARM and Synopsys
- Algorithm to System-on-Chip Design Flow that Leverages System Studio and SystemC 2.0.1, STMicroelectronics
February 2004 - Highlights:
- How to Get Started with SystemVerilog Assertions
- A Reference Verification Methodology for Vera
- The Dangers of Living with a X (bugs hidden in your Verilog), ARM
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