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| User Papers and Presentations |
| A1 - Verification Modeling and Reuse |
A Generic and Reusable VMM Based CPU Verification Environment in SystemVerilog
Author(s): Michael Roeder, Christian Glassner, Wolfgang Hoeld [National Semiconductor GmbH, Germany] Fabian Delguste [Synopsys Europe] |
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Reusable DMA Verification
Author(s): Joachim Geishauser, Daniel Hoheisel, Yijing Lui, Terry Gong [Freescale Semiconductor, Inc.] |
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Using Operating System Modeled in SystemVerilog to Enhance System Verification
Author(s): Remi Francard [STMicroelectronics], Roger Ninane [Synopsys Europe] |
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| A2 - Advanced STA |
How to Complete Sign-off STA and Timing Closure in Advanced 65nm Process
Author(s): Stephane Cerone [Texas Instruments], Pascal Coffin [Synopsys Europe] |
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Post-processing of Static Timing Analysis Reports
Author(s): Thomas Niedermeier [Infineon Technologies] |
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Static Timing Verification for Complex SoC Design - Application of "Internal Path" Approach
Author(s): Ahaneku Ogu , Qu Fu Yang [Infineon Technologies] |
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| A3 - IP Integration and Verification |
Library Generation for Backend Tools - The Frustrations, Hazards, Hidden Costs and How to Avoid Them
Author(s): Stefan Reif, Charles Fowler [Infineon Technologies] |
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SPIRIT-based IP Assembly and SDC Promotion for a 65nm System-on-Chip using coreAssembler
Author(s): Olivier Florent, Philip Cuney, Cyril Vartanian [STMicroelectronics], Emanule Irrera, Sal Tiralongo, Stéphane Maulet [Synopsys Europe] |
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| A4 - Advanced Design Flows for Shorter Time-to-Market |
An Efficient Script-based RTL-to-GDSII Flow using the Jupiter-XT - PC - Astro Tool Chain in 130 nm on a 350K-instance Design
Author(s): Pierre-Marie Signe [Abilis Systems], John Lofgren [Synopsys, Inc.] |
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Automated ECO flow using Synopsys’ Formality and Design Compiler
Author(s): Fabien Camus, Jerome Bombal [Texas Instruments France] |
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Push Button Flow for Mixed Signal Designs using Recommended Astro™ Script-Based Methodology
Author(s): Michael Lortz, Martin Embacher [National Semiconductor], Frank Schlegel [Synopsys Europe] |
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| A5 - Saber I |
Automotive Single Core Wire Examination with SaberHDL and VHDL-AMS
Author(s): Manfred Klinkenberg [Yazaki Europe Ltd.] |
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FlexRay – Simulation of Physical Layer Topologies
Author(s): David Bollati - C&S Group, Fachhochschule [University of Applied Sciences] |
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ISET-LAB Lead Acid Battery Simulation Software - Integration into Saber
Author(s): Peter Caselitz, Dirk Lehmkuhl [Institut für Solare Energieversorgungstechnik e. V.] |
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| B2 - DFT Compiler Max - State of the Art Usage |
Applying Scan Compression with One Single Test-Input
Author(s): Paul Armagnat [STMicroelectronics] |
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DFT Compiler MAX Trials on a Bottom-up Built SoC
Author(s): Vincent Chalendard, Michael Rodat [Texas Instruments, Inc.] |
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Dual Scan Compression Architecture using DFTMax
Author(s): Marco Casarsa [STMicroelectronics] |
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| B3 - Sign-off with Physical Implementation |
Crosstalk Repair Flow for Timing Closure in Very Deep Submicron Designs
Author(s): Bernhard Obermayer, Hendrik T. Feldkaemper [Micronas GmbH] |
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Embedded Flash Power Grid Sign-off using PrimeRail TX
Author(s): Thomas Röhr, Yannick Martelloni, Thomas Baumann, Markus Kuhn [Infineon Technologies AG] |
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Static Power Net Integrity Analysis on STMicroelectronics Set Top Box Products
Author(s): Jean Jimenez [STMicroelectronics], Emmanuel Pluchart [Synopsys Europe] |
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| B4 - Low Power Design and Power Supply Methodologies |
MultiVoltage Implementation Flow with Synopsys Tools (Technical Committee Award)
Author(s): Rainer Mann, Karsten Matt [AMD] |
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Rectilinear Supply Mesh Insertion using JupiterXT Virtual Flat Flow (3rd Place - Best Paper)
Author(s): Stephanie D. Miller [ARM Inc.], Abid M. Jindani [Synopsys Inc.] |
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| B5 - Saber II |
Automating the Process of Test Bench Generation, Simulation and Documentation Generation using AIM, Saber & Latex (2nd Place - Best Paper)
Author(s): Dr Peter R. Wilson [Integra Design Ltd, UK] |
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Design of the Electrical System for a Fuel Cell Hybrid Vehicle
Author(s): Hartmut Hinz [Adam Opel GmbH] |
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System Optimization using SABER within the MOSCITO Framework
Author(s): Peter Schneider, André Schneider, Peter Schwarz, Jens Bastian [Fraunhofer Institute for Integrated Circuits] |
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| C1 - SystemVerilog |
Assertion-based Verification with SystemVerilog
Author(s): Gábor Dudás, Wenhao Yan, Richard Willems [Deutsche Thomson-Brandt GmbH] |
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Interfacing C Functional Verification Stimuli with Verilog, OpenVera and SystemVerilog
Author(s): Walter Soto Encinas Junior, Alex Rocha Prado [Freescale Semiconductor] |
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Using SVA with VCS for Mixed-Language Verification
Author(s): Simon Hohenstern, Sonja Schneider, Bernhard Niemann [Fraunhofer Institute for Integrated Circuits] |
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| C2 - DFT Technologies |
Flash Memory's Control Logic Structural Test
Author(s): Vincenzo Matranga, Vincenzo Marino, Rosanna Badalamenti, Carmelo Chiavetta [STMicroelectronics], Salvatore Talluto [Synopsys Europe] |
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| C5 - Saber III |
Development, Validation and Prediction of ATV Energy Management with a Coupled Power, Thermal and On-board Software Simulator
Author(s): R. Ameziane, J-Ch. Guyot, J-P. Hulier, L. Juve, H. Monar, P. Oger [EADS - Space Transportation] |
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Evaluation of the Electrical Machine Performance by Magnetic Network Analysis
Author(s): Karsten Schönherr, Anton Paweletz [Robert Bosch GmbH] |
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| E1 - Block/Subsystem Level Verification |
A Bottom-up Approach to Top-down VMM
Author(s): Xavier Caron [Atmel] |
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Verification of Graphics Algorithms using VERA
Author(s): Syed Ubaidullah Hussaini, Holger Bellm, Axel Klein, Roland Frei, [Toshiba Electronics Europe GmbH] |
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VHDL to SystemVerilog: Constrained Random Verification of a USB 2.0 Host Controller Sub-System
Author(s): Richard McGee, Paul Furlong [Silicon & Software Systems (S3)], Fabian Delguste [Synopsys Europe] |
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| E5 - Mixed-Signal Design Verification with NanoSim & NanoSim-VCS |
AMS Transistor Level Simulation Resolving Timing Issues With A Traditional Digital Design Flow
Author(s): Louis Frew [Atmel] |
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Managing Simulations with HSIM GUI
Author(s): Rom Bronfman [Saifun Semiconductors Ltd] |
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NOR and NAND Flash Cell Built-in Model Specification, Implementation and Validation in the NanoSim Simulator
Author(s): Pierluigi Daglio, Davide Lena [STMicroelectronics] |
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| F2 - Power |
Automated Design Modification Flow to Reduce Power During Scan Shifting using Synopsys' Design Compiler
Author(s): Carole Brusson, Christophe Vergnet, Jerome Bombal [Texas Instruments France] |
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Power Optimised Digital Filterbank as Part of a Psychoacoustic Human Hearing Model
Author(s): Frank Poppen, Milan Schulte, Wolfgang Nebel [OFFIS] |
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| F3 - Using SystemVerilog in a Design Flow |
Modeling with SystemVerilog in a Synopsys Synthesis Design Flow Using Leda, VCS, Design Compiler and Formality (1st Place - Best Paper)
Author(s): Stuart Sutherland [Sutherland HDL, Inc.] |
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SystemVerilog Assertions are for Design Engineers Too!
Author(s): Stuart Sutherland [Sutherland HDL, Inc.], Don Mills [LCDM Engineering] |
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| F4 - System Level Design / Library Correlation |
Library Gotchas – Guidelines for Physical Library Qualification
Author(s): Lavanya Murugesan, Tamiko Yoneyama, Koshi Matsushita [Synopsys, Inc.] |
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Virtual Prototyping for a 3G Baseband Chip Based on VaST CoMET / Synopsys System Studio Cosimulation (Best First-Time Presenter)
Author(s): Stefan Heinen, Mario Steinert [Infineon Technologies AG] |
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| Managers' Track |
Design to the Rescue of the Silicon Roadmap
Author(s): Marco Casale-Rossi [Synopsys, Inc.] |
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Functional Verification from a Manager's Perspective: When is Good Enough, Really Good Enough?
Author(s): Ira Chayut [NVIDIA Corp] |
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Low Power: By Design or by Accident?
Author(s): Keith Clarke [ARM Limited] |