| Time | Description |
| 8:30-9:30 | Registration and Breakfast |
| 9:30-10:15 | |
| 10:15-10:30 | Break |
 | Front-end Implementation  | Digital Verification | Physical Design
& Sign-off | Design for Test | Custom Design & AMS Verification
| System Level & FPGA
|
| 10:30-12:00 | A1 User & Tutorial
Low-Power Implementation and Constraint Checking | A2 Tutorial & User
RTL Verification - Testbench Automation | A3 User Session
Advanced Physical Design Flows | A4 User Session
Design for Test & ATPG I | A5 User & Tutorial
AMS & Full Custom Design | A6 User & Vision Session
High Level Synthesis & FPGA Vision |
| 12:00-13:15 | Lunch |
| 13:15-14:45 | B1 User & Demo
Back-End Integration to Synthesis | B2 User & Tutorial
Low-Power Verification | B3 User & Tutorial
Physical Design: Timing Closure | B4 User Session
Design for Test & ATPG II | B5 User & Tutorial
AMS Design & Verification | B6 User & Tutorial/Demo
FPGA Design & Prototyping |
| 14:45-15:15 | Break |
| 15:15-16:45 | C1 Combo Session
Front-End Design Exploration | C2 User & Tutorial
System Level Verification | C3 Tutorial
Hierarchical Physical Design & Exploration | C4 Tutorial
Design for Test & Yield Improvement | C5 User & Tutorial
Advanced Mixed-Signal Verification | C6 User & Tutorial/Demo
Advanced FPGA-based Prototyping |
| 16:45-18:00 | Best Paper Awards and Refreshments |